Mixed baseband architecture based on FBD ΣΔ–based ADC for multistandard receivers

Abstract

This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4^th order single-bit Sigma-Delta modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.