A cost-efficient reversible logic gates implementation based on measurable quantum-dot cellular automata
In order to improve the density on a chip, the scaling of CMOS-based devices begins to shrink in accordance with Moore's laws. This scale affects the execution of the CMOS device due to specific limitations, such as energy dissipation and component alignment. Quantum-dot cellular automata (QCA) have been replaced to overcome the inadequacies of CMOS technology. Data loss is a major risk in irreversible digital logic computing. As a result, the market for nano-scale digital operations is expanding, reducing heat dissipation. Reversible logic structures are a strong competitor in the creation of efficient digital systems. A reversing logic gate is an important part of reversible circuit design. The QCA design of basic reversible logic gates is discussed in this study. These gates are built using a new QCA design with XOR gates with two and three inputs. QCADesigner tests simulation performance by simulating the specified reversible logic gate layouts. The measurement and optimization of design techniques at all stages is required to reduce power, area, and enhance speed. The work describes experimental and analytic approaches for measuring design metrics of reversible logic gates using QCA, such as ancilla input, garbage output, quantum cost, cell count, and area, while accounting for the effects of energy dissipation and circuit complexity. The parameters of reversible gates with modified structures are measured and then compared with the existing designs. The designed F2G, FRG, FG, RUG and UPPG reversible logic gates using QCA technology shows an improvement of 42 %, 23 %, 50 %, 39 % and 68 % in terms of cell count and 31 %, 20 %, 33 %, 20 % and 72 % in terms of area with respect to the best existing designs. The findings illustrate that the proposed architectures outperform previous designs in terms of complexity, size, and clock latency.
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